[RISCV] Introduce RVI AME (standard, pre-ratification) backend support by vismaysur · Pull Request #22 · RuyiAI-Stack/llvm-project

vismaysur · 2026-07-14T04:52:22Z

This PR adds initial RISC-V AME backend support.

Tasks/Deliverables:

target feature support (subtarget features for AME_NUM_M_REGS and AME_NUM_ACC_REGS)
matrix register definitions
instruction definitions + encodings
intrinsics
tests: llc (.ll -> .s and .ll -> .o) and llvm-mc (.s -> .o).

Closes #21

github-actions · 2026-07-14T04:52:38Z

Thank you for submitting a Pull Request (PR) to the LLVM Project. Since this is your first PR, here are a few useful links covering our main contribution policies and review practices.

All contributions to LLVM must follow our LLVM AI Tool Use Policy. In particular, if you used AI while working on this PR, remember to add a note to the PR description.
The LLVM Code-Review Policy and Practices document contains practical information about the PR process, including how patches are reviewed and accepted, and who can review a PR.
Our LLVM Developer Policy describes our expectations for code quality, commit summaries and contains notes on our CI system.

Please reply to this message to confirm that you have read these policies, especially the LLVM AI Tool Use Policy, and that any AI tool usage has been noted in the PR description.

Frequently asked questions

How do I add reviewers?

This PR will be automatically labeled, and the relevant teams will be notified. For some parts of the project, reviewers may also be added automatically.

You can also add reviewers manually using the Reviewers section on this page. If you cannot use that section, it is probably because you do not have write permissions for the repository. In that case, you can request a review by tagging reviewers in a comment using @ followed by their GitHub username.

What if there are no comments?

If you have not received any comments on your PR after a week, you can request a review by pinging the PR with a comment such as “Ping”. The common courtesy ping rate is once a week. Please remember that you are asking for volunteer time from other developers.

Are any special GitHub settings required to contribute to LLVM?

We only require contributors to have a public email address associated with their GitHub commits, see this section of LLVM Developer Policy for details.

If you have questions, feel free to leave a comment on this PR, or ask on LLVM Discord or LLVM Discourse.

Thank you,
The LLVM Community

vismaysur · 2026-07-14T20:01:15Z

A few important observations / notes:

mls.rm / mls.cm / mls instructions (for loading squares) have no stride operands (encoding only the destination reg index and the base mem addr). so they can only load tiles that are already contiguous in memory (rather than extracting tiles out of a larger strided row-major / column-major matrix).

Just a detail to keep note of: if a stride operand is later added to the spec, we will not need to repack data in memory into tiles.

zhanghb97 · 2026-07-22T05:14:26Z

A few important observations / notes:

mls.rm / mls.cm / mls instructions (for loading squares) have no stride operands (encoding only the destination reg index and the base mem addr). so they can only load tiles that are already contiguous in memory (rather than extracting tiles out of a larger strided row-major / column-major matrix).

Just a detail to keep note of: if a stride operand is later added to the spec, we will not need to repack data in memory into tiles.

Good catch. We will keep our design aligned with the RVI specification and make the corresponding changes if the specification is updated.

zhanghb97 · 2026-07-22T05:16:40Z

Please rebase the PR. I will start the review today.

vismaysur · 2026-07-22T05:32:25Z

Note: BOSCAME backend seems to instruction select LLVM IR to pseudo instructions (with immediate operands) which are then directly printed as asm, with no path (as i understand it) to MCInstr encodings / .o output. it has real instruction encodings but these are only reachable from .s or .o inputs, not from LLVM IR (please clarify if my understanding is incorrect).

Since M/Acc indices are already assigned by MLIR before they reach LLVM, so encoding them as immediates (rather than encoding register class operands) lets ISel lower straight to the real, bit-encoded instruction. I took a slightly different path in this backend of omitting the pseudo instructions altogether, instead encoding real instructions with immediate operands, enabling a single path from LLVM IR -> MCInstr with real encodings -> both .o and .s outputs.

…th immediates

zhanghb97

@vismaysur, I listed the problems I found.

cc @Yranger, there are some changes regarding BOSC AME that need to be reviewed.

zhanghb97 · 2026-07-23T23:43:48Z

+  static const unsigned Regs[] = {RISCV::BOSCAMETR0, RISCV::BOSCAMETR1,
+                                  RISCV::BOSCAMETR2, RISCV::BOSCAMETR3,
+                                  RISCV::BOSCAMETR4, RISCV::BOSCAMETR5,
+                                  RISCV::BOSCAMETR4, RISCV::BOSCAMETR7};


RISCV::BOSCAMETR4 -> RISCV::BOSCAMETR6

zhanghb97 · 2026-07-23T23:45:50Z

@@ -0,0 +1,585 @@
+//===- RISCVInstrInfoZtt.td - 'Ztt' ----------*- tablegen -*-===//


Wrong format: 80-column

zhanghb97 · 2026-07-23T23:50:04Z

+    bits<5> xs1;
+    bits<2> ad;
+
+    let Inst{19 - 15} = xs1;


Inst{24 - 20} has not been set.

zhanghb97 · 2026-07-24T00:05:12Z

+  // Moves
+  def : Pat<(int_riscv_ztt_mmov_a_m timm:$md, timm:$acc), (ZTT_MMOV_A_M timm:$md, timm:$acc)>;
+  def : Pat<(int_riscv_ztt_mmov_m_m timm:$md, timm:$ms), (ZTT_MMOV_M_M timm:$md, timm:$ms)>;
+  def : Pat<(int_riscv_ztt_mshift_ew timm:$md, timm:$ms1, timm:$imm), 


llvm.riscv.ztt.mshift.m1 and llvm.riscv.ztt.mshift.p1 are declared in llvm/include/llvm/IR/IntrinsicsRISCVStdExtZtt.td, but there are no corresponding ISel patterns in this file.

According to the AME specification, mshift.m1 and mshift.p1 are aliases of mshift.ew with immediate values -1 and 1, respectively. Please either:

add lowering patterns that select them to ZTT_MSHIFT_EW

or:

remove the two LLVM intrinsics and model them only as assembler aliases using InstAlias.

The second option may be preferable because these are aliases rather than independent instructions.

Please also add CodeGen tests covering both intrinsics if they remain exposed through LLVM IR.

zhanghb97 · 2026-07-24T00:15:15Z

@vismaysur Please use clang-format to format all files and check the license header formatting.

WuXintong123 force-pushed the riscv branch from f3c607b to 8e108fd Compare July 14, 2026 05:40

vismaysur force-pushed the feature/rvi-ame-backend branch 7 times, most recently from 12d2b78 to 36036f7 Compare July 16, 2026 02:06

vismaysur changed the title ~~[RISCV] Introduce RVI AME (standard, pre-ratification) intrinsics~~ [RISCV] Introduce RVI AME (standard, pre-ratification) backend support Jul 16, 2026

WuXintong123 force-pushed the riscv branch 2 times, most recently from e7c4297 to 8d7801d Compare July 17, 2026 16:34

vismaysur force-pushed the feature/rvi-ame-backend branch from b1e3edf to 5c844e7 Compare July 18, 2026 00:55

WuXintong123 force-pushed the riscv branch from 8d7801d to 050f388 Compare July 18, 2026 17:10

vismaysur force-pushed the feature/rvi-ame-backend branch from 5c844e7 to c28b72e Compare July 19, 2026 15:34

WuXintong123 force-pushed the riscv branch from 050f388 to ef209ae Compare July 19, 2026 17:02

vismaysur marked this pull request as ready for review July 19, 2026 21:48

vismaysur mentioned this pull request Jul 19, 2026

[TASK] Add Initial RISC-V AME Support to LLVM #21

Open

WuXintong123 force-pushed the riscv branch from ef209ae to 489cbe8 Compare July 20, 2026 02:40

vismaysur force-pushed the feature/rvi-ame-backend branch from b5dac9e to a4a3978 Compare July 20, 2026 04:41

WuXintong123 force-pushed the riscv branch from 489cbe8 to fb865cb Compare July 20, 2026 16:59

vismaysur force-pushed the feature/rvi-ame-backend branch from a4a3978 to 2cc830c Compare July 21, 2026 02:39

vismaysur temporarily deployed to riscv64 July 21, 2026 10:44 — with GitHub Actions Inactive

WuXintong123 force-pushed the riscv branch from fb865cb to 07f6017 Compare July 21, 2026 16:07

vismaysur force-pushed the feature/rvi-ame-backend branch from 2cc830c to b9c7652 Compare July 22, 2026 05:22

WuXintong123 force-pushed the riscv branch from 07f6017 to 8bfce84 Compare July 22, 2026 16:29

vismaysur force-pushed the feature/rvi-ame-backend branch from b9c7652 to 1cba266 Compare July 22, 2026 19:49

WuXintong123 force-pushed the riscv branch from 8bfce84 to c56414b Compare July 23, 2026 16:36

vismaysur added 10 commits July 23, 2026 17:03

[RISCV] Introduce RVI AME (standard, pre-ratification) intrinsics

4657306

[RISCV: Refactor] Reorganize all AME register definitions

19a1b1b

[RISCV: Feat] Add AME(Ztt) instruction defs and encodings

69c120d

[RISCV: Refactor] Remove AME(Ztt) register definitions and replace wi…

d42ddf8

…th immediates

[RISCV: Feat] Add ISel pattern matching for LLVM IR -> MachineInstrs

5e51d3d

[RISCV: Feat] Constraint AME Matrix and Acc Reg Indices

1a5da91

[RISCV: Fix] feature support

434408f

[RISCV: Feat] Fix operand naming, tests etc.

6de1d13

[RISCV: Fix] Remove unnecessary changes

76b5579

[RISCV: Feat] Added tests for subtarget misconfigs

9cd2449

vismaysur force-pushed the feature/rvi-ame-backend branch from 1cba266 to 9cd2449 Compare July 23, 2026 17:04

zhanghb97 reviewed Jul 24, 2026

View reviewed changes

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[RISCV] Introduce RVI AME (standard, pre-ratification) backend support#22

[RISCV] Introduce RVI AME (standard, pre-ratification) backend support#22
vismaysur wants to merge 10 commits into
RuyiAI-Stack:riscvfrom
vismaysur:feature/rvi-ame-backend

vismaysur commented Jul 14, 2026 •

edited

Loading

Uh oh!

github-actions Bot commented Jul 14, 2026

Uh oh!

vismaysur commented Jul 14, 2026 •

edited

Loading

Uh oh!

zhanghb97 commented Jul 22, 2026

Uh oh!

zhanghb97 commented Jul 22, 2026

Uh oh!

vismaysur commented Jul 22, 2026

Uh oh!

zhanghb97 left a comment •

edited

Loading

Uh oh!

zhanghb97 Jul 23, 2026

Uh oh!

zhanghb97 Jul 23, 2026

Uh oh!

zhanghb97 Jul 23, 2026

Uh oh!

zhanghb97 Jul 24, 2026

Uh oh!

zhanghb97 commented Jul 24, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

		@@ -0,0 +1,585 @@
		//===- RISCVInstrInfoZtt.td - 'Ztt' ----------- tablegen --===//

Uh oh!

Conversation

vismaysur commented Jul 14, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

github-actions Bot commented Jul 14, 2026

Frequently asked questions

Uh oh!

vismaysur commented Jul 14, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

zhanghb97 commented Jul 22, 2026

Uh oh!

zhanghb97 commented Jul 22, 2026

Uh oh!

vismaysur commented Jul 22, 2026

Uh oh!

zhanghb97 left a comment • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

zhanghb97 Jul 23, 2026

Choose a reason for hiding this comment

Uh oh!

zhanghb97 Jul 23, 2026

Choose a reason for hiding this comment

Uh oh!

zhanghb97 Jul 23, 2026

Choose a reason for hiding this comment

Uh oh!

zhanghb97 Jul 24, 2026

Choose a reason for hiding this comment

Uh oh!

zhanghb97 commented Jul 24, 2026

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

vismaysur commented Jul 14, 2026 •

edited

Loading

vismaysur commented Jul 14, 2026 •

edited

Loading

zhanghb97 left a comment •

edited

Loading